1. Field of the Invention
The present invention relates to a method and related apparatus for clearing data in a memory, and more particularly, to a method and related apparatus for clearing data in a memory without the involvement of a CPU.
2. Description of the Prior Art
FIG. 1 is a schematic diagram of a conventional computer system 10. As shown in FIG. 1, the computer system 10 includes a CPU 12, a north bridge circuit 14, a south bridge circuit 16, a display controller 18, a display 19, a memory 20, a hard disk 22, and an input device 24. The memory 20 includes a plurality of memory units 26 arranged in arrays, i.e., each memory unit 26 corresponds to a column address and a row address. The accessing operations of the memory 20 are controlled via a memory controller 30 positioned in the north bridge circuit 14. The memory controller 30 includes an address register 32 and a data register 34 where the address register 32 is for storing memory addresses, and the data register 34 is for storing data to be written to the memory 20 and data read from the memory 20.
For the computer system 10, any executed programs, for example a driver or an application program, require the memory 20 for storing data. When a first application program is executed, a memory block of the memory 20 is designated for storing operation data of the first application program. While the first application program is closed, the memory block must be released so that other programs can use this memory block to store data. In addition to release the memory block, however, the first application program must clear the memory block, by for example overwriting the data stored in each memory unit 26 of the memory block with a logic value “1” or “0”. In such case, a second application program executed thereafter, can correctly access data in the same memory block. If that memory block is not cleared, errors due to misjudgment may occur when the second application program is executed. These errors may even lead to the crash of the computer system 10.
Therefore, when a program requires a certain capacity of memory units 26 in the memory 20 to store operation data, that certain capacity of memory units 26 must be overwritten with logic values “1” or “0”. For example, if the CPU 12 executes the program codes of clearing data, the CPU will output the memory addresses corresponding to the memory units 26 to be used to the address register 32. Meanwhile, the CPU 12 will repeatedly output the logic value “1” or “0” to the data register 34. If the capacity of the memory 20 to be used is 3 MB, the CPU 12 will output the logic values “1” to the data register 34 24 million times for clearing 24 million memory units 26 (corresponding to 3 MB capacity) in the memory 20. It can be seen that the CPU 12 spends much time repeatedly outputting the logic value “1” or “0” to the memory 20, thereby reducing its efficiency. In addition to reducing the efficiency of the CPU 12, the limited bandwidth of the front-side bus (FSB) between the CPU 12 and the north bridge circuit 14 is also consumed. This also affects the total efficiency of the computer system 10.